1M Tech VLSI Projects Title 2014
2A Novel VLSI DHT Algorithm for a Highly
Modular and Parallel Architecture
3.
A Novel Approach for Parallel CRC generation
for high speed application Design ofHigh Performance 64 bit MAC Unit
4.
RADIX 10 PARALLEL Decimal Multiplier
5.
A higher radix FFT FPGA implementation
suitable for OFDM systems
6. A Distributed Canny Edge Detector: Algorithm and FPGA Implementation
7. Performance analysis of FPGA based Sobel edge detection operator
8. Vehicle image edge detection algorithm hardware implementation on FPGA
9. An FPGA Implementation of Gradient Based Edge Detection Algorithm Design
10. Hardware implementation of truncated multiplier based on multiplexer using FPGA
11. FPGA implementation of high speed 8-bit Vedic multiplier using barrel shifter
12. CSD(Canonical signed digit) multipliers for FPGA DSP applications
13. Enhanced Memory reliability against multiple cell upset using decimal matrix code
14. A Simple Pipelined Logarithmic Multiplier
15. Design and implementation Reversible BCD adder
16. High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics
17. A High-speed 32-bit Signed/Unsigned Pipelined
Multiplier
18. FPGA based data acquisition and analysis system
19. Design and implementation of truncated multipliers for precision improvement
20. Design ofHigh Performance 64 bit MAC Unit
21. High-Throughput Compact Delay-Insensitive Asynchronous NoC Router
22. Performance evaluation of FPGA based crossbar NoC architecture
23. Design
of AES (Advanced Encryption Standard) Encryption and Decryption IP core
24. FPGA
Implementation of IRDA IP core
25. Design
of JPEG Image compression standard
26. FPGA
Implementation of Triple DES
27. FPGA
Implementation of DES
28. Pipelined
Parallel FFT Architectures via Folding Transformation
29. Implementation
of Radix2 ACS in Adaptive Viterbi decoder
30. Analysis, Verification And FPGA Implementation Of
Vedic Multiplier
No comments:
Post a Comment